1. Field of the Invention
The present invention relates to a method for plating gold to bond leads on a semiconductor substrate, more particularly, to a gold plating method which extends a plating line to the bond area of the substrate to electrically connect the bond leads together thereby plating gold thereto.
2. Description of Related Art
In the semiconductor packaging process, the bond lead, which is used to electrically connect a die with a substrate, is usually plated with gold to increase the anti-corrosion and electrical conductivity properties. FIG. 4 shows a conventional arrangement for plating gold to the bond leads (41) on a substrate (40). Each bond lead (41) has one end located at the bond area (42), which is an empty area at the center portion of the substrate (40). The other end of each bond lead (41) is connected with a ball land (43). In order to plate gold to the bond leads (41) and the ball lands (43), a plating loop (44) is provided on the edge of the substrate (40). The plating loop (44) has a plurality of plating lines (441) extended therefrom, each being connected to a bond lead (41) and a corresponding ball land (43). Consequently, the bond leads (41) and ball lands (43) can be plated with gold by conducting electricity thereto via the plating loop (44) and the plating lines (441). When such the gold plating step is completed, as shown in FIG. 5A, the semiconductor packaging process is undertaken by executing a die attachment step, wherein the die (51) is attached to the substrate (40). Then, as shown in FIG. 5B, a cutting and bonding step is processed, wherein a bonding tool (52) is provided to cut off the bond leads (41) (if required) and connect the bond leads (41) to the solder pads (511) on the die (51). Afterwards, as shown in FIG. 5C and 5D, an encapsulation step and a ball mount step are processed to encapsulate the die (51) with encapsulation material (53) and mount a solder ball (54) on each of the ball lands (43). Finally, referring to FIG. 4 and FIG. 5E, a separation step is executed by cutting off the substrate (40) along the separation line (45) thereby producing a packaged semiconductor chip.
As described above, the substrate (40) of the conventional semiconductor chip has a plurality of plating lines (441) extended from the plating loop (44) toward the bond area (42) thereof for plating gold to the bond leads (41) and ball lands (43). Because these extended plating lines (441) are formed on the surface of the substrate (40), the surface area of the substrate (40) that can be used for circuit layout is restricted. Furthermore, when the substrate (40) is cut off along the separation line (45), there are still lots of residual plating lines (441) on the substrate (40). These residual plating lines (441) may cause the packaged semiconductor chip to have bad electrical performance and capacitive crosstalk. An antenna effect is also raised because of the residual plating lines (441) when the packaged semiconductor chip is operated at a high frequency. As a result, the performance of the semiconductor chip can not be promoted. Therefore, there is a need for the above gold plating method to be improved.